? semiconductor components industries, llc, 2001 june, 2001 rev. 5 1 publication order number: mc100elt23/d mc100elt23 5vdual differential pecl to ttl translator the mc100elt23 is a dual differential pecl to ttl translator. because pecl (positive ecl) levels are used, only +5 v and ground are required. the small outline 8-lead package and the dual gate design of the elt23 makes it ideal for applications which require the translation of a clock and a data signal. the pecl inputs are differential; therefore, the mc100elt23 can accept any standard differential pecl input referenced from a v cc of 5.0 v. ? 3.5 ns typical propagation delay ? 24 ma ttl outputs ? flow through pinouts ? esd protection: >2 kv hbm, > 400 v mm ? the 100 series contains temperature compensation ? operating range v cc = 4.75 v to 5.25 v with gnd= 0 v ? internal input pulldown resistors ? q output will default high with inputs left open or < 1.3 v ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 91 devices 1 2 3 45 6 7 8 q0 gnd v cc d0 q1 d1 d1 d0 pecl ttl pin function qn ttl outputs dn, dn pecl differential inputs v cc positive supply gnd ground pin description figure 1. 8lead pinout and logic diagram (top view) http://onsemi.com device package shipping ordering information mc100elt23d so8 98 units / rail mc100elt23dr2 so8 2500 / reel mc100elt23dt tssop8 98 units / rail mc100elt23dtr2 tssop8 2500 / reel *for additional information, see application note and8002/d so8 d suffix case 751 marking diagrams* tssop8 dt suffix case 948r a = assembly location l = wafer lot y = year w = work week 1 8 1 8 alyw klt23 1 8 alyw kt23 1 8
mc100elt23 http://onsemi.com 2 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc power supply gnd = 0 v 7 v v i input voltage gnd = 0 v v i v cc 0 to 6 v i g i cc v ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w q jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w q jc thermal resistance (junction to case) std bd 8 tssop 41 to 44 5% c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. pecl input dc characteristics v cc = 5.0 v; gnd= 0.0 v (note 2) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v ih input high voltage (single ended) 3835 4120 3835 4120 3835 4120 mv v il input low voltage (single ended) 3190 3525 3190 3525 3190 3525 mv v ihcmr input high voltage common mode range (differential) (note 3) 2.2 5.0 2.2 5.0 2.2 5.0 v i ih input high current 150 150 150 m a i il input low current 0.5 0.5 0.5 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input parameters vary 1:1 with v cc . v cc can vary 0.25 v. 3. v ihcmr min varies 1:1 with gnd, v ihcmr max varies 1:1 with v cc . ttl output dc characteristics v cc = 4.75v to 5.25v; t a = 40 c to 85 c symbol characteristic condition min typ max unit v oh output high voltage i oh = 3.0 ma 2.4 (note 4) v v ol output low voltage i ol = 24 ma 0.5 v i cch power supply current 23 33 ma i ccl power supply current 26 36 ma i os output short circuit current 150 60 ma 4. max level is v cc 0.7 v by design. ac characteristics v cc = 5.0 v; gnd= 0.0 v (note 5 and note 6.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd mhz t jitter cycletocycle jitter tbd tbd tbd ps t plh propagation delay @ 1.5 v c l = 20 pf 2.0 5.5 2.0 5.5 2.0 5.5 ns t phl propagation delay @ 1.5 v c l = 20 pf 2.0 5.5 2.0 5.5 2.0 5.5 ns v pp input swing (note 7) 200 1000 200 1000 200 1000 mv t r /t f output rise time (1090%) c l = 20pf output fall time (1090%) c l = 20pf 1.6 1.1 ns ns 5. v cc can vary 0.25 v. 6. all loading with 500 ohms to gnd, cl = 20 pf. 7. v pp (min) is the minimum input swing for which ac parameters are guaranteed. the device has a dc gain of 40.
mc100elt23 http://onsemi.com 3 figure 2. ttl output loading used for device evaluation ttl driver receiver qd ttl 500 gnd r l c l * * 20 pf total cap ac load (includes fixture) resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1560 low voltage eclinps spice modeling kit an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc100elt23 http://onsemi.com 4 package dimensions so8 d suffix plastic soic package case 75107 issue v seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc100elt23 http://onsemi.com 5 package dimensions tssop8 dt suffix plastic tssop package case 948r02 issue a dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016
mc100elt23 http://onsemi.com 6 notes
mc100elt23 http://onsemi.com 7 notes
mc100elt23 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100elt23/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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